Display device for electronic calculator or the like

ABSTRACT

A display device disclosed herein includes a dot matrix type liquid crystal display panel capable of displaying not only digits but characters in the form of a matrix. Digit of character information is stored within a memory forming part of a CPU and shifted digit by digit or character by character while the display device is in operation. In other words, the digits or characters are shifting or running at each given length of time. The present device makes it possible of displaying numerals, characters, symbols and the like of a length more than the capacity of the display panel.

BACKGROUND OF THE INVENTION

This invention relates to a display device for use in an electronic apparatus such as an electronic calculator, and more particularly a new and effective display device for displaying data derived from an electronic calculator.

In the past, when it was desired to display data having a length more than the capacity of a display panel in an electronic calculator, the data to be displayed would be split into two or more groups in advance. Nevertheless, the connection between the groups was often indefinite and vague, leading to operator errors in recognizing the overall or combined contents being displayed.

OBJECTS AND SUMMARY OF THE INVENTION

It is therefore an object of the present invention to surmount the above discussed difficulties with the prior art. It is another object of the present invention to provide a display device for use in electronic calculators or the like which is capable having displaying data of a length more than the capacity of a display panel by shifting the overall display contents such as numerals, characters and symbols at every passage of a given length of time. The above discussed difficulties are overcome by constantly moving the display contents without switching the display contents at the conclusion of each group, thereby enhancing legibility of the display contents.

One of the features of the present invention lies in that the display contents are shifted and circulated in such a manner that the beginning of the display contents are again displayed after the overall display contents have gone from the edge of the display panel. In other words, the beginning of the display contents is not displayed unless the overall contents disappear from the edge of the panel. The display device according to the present invention provides an easy to read display with a definite delimitation.

Another feature of the present invention is that the displaying operation is accomplished in either a conventional mode (namely, the static mode) or a shift mode, depending upon what kind of data is to be displayed. Fr example, data such as operation results are displayed in the conventional mode (the static mode), whereas instructions as to the order of arithmetic operations are displayed in the shift mode and thus the instructions being displayed are moved at every passage of the given length of time. Even though the same contents are displayed on the panel, it becomes possible to identify the significance (or the type) of the contents by the displaying condition. This feature of the present invention is very instrumental to multiple function calculators.

As still another advantageous feature, the prevent invention provides a display device for an electronic calculator with various facilities: displaying in a similar manner to talking-news on buildings data to be next introduced when the calculator is in a halt condition on the way of executing program calculations (that is, a particular calculation comes to a halt until data are entered at a step of entering data from outside of the calculator on the way of executing the calculation); modifying characters (symbols) at a particular region of the overall display contents according to the internal operating state of the calculator; and also displaying calculation results for a given length of time immediately before the display state is commenced.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and for further objects and advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a plan view of an example of a programmable calculator embodying a display device according to the present invention;

FIG. 2 is an explanatory diagram of the progress of the displaying state of the calculator;

FIG. 3 is a schematic block diagram showing the essence of the calculator;

FIGS. 4A, 4B, 4C and 4D are logic diagrams of an example of a central processor unit (CPU) in the calculator;

FIG. 5 is a composite schematic diagram of the CPU in the calculator;

FIG. 6 is a flow chart for explaining the displaying operation according to the present invention; and

FIG. 7 is a flow chart for explaining the left shift operation of a character memory MC.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In FIGS. 1 and 2, there are illustrated a plan view of a programmable calculator according to one preferred embodiment of the present invention and a representation showing the progress of the display state of the calculator.

In FIG. 1, a display device, for example, a dot matrix type alphanumerical liquid crystal display panel is labeled 1 and a keyboard unit is labeled 2. FIGS. 2(a)-2(i) show events over the progress of the display state when a calculator such as a function calculator reaches a halt condition during the progress of calculations to instruct the operator to introduce input data to be next introduced. FIG. 2(a) depicts a normal display mode whereas FIGS. 2(b)-2(g) depict a shifting or running display at respective points in time according to the present invention. In FIG. 2(a), there is displayed the leading character of an instruction indicative of introduction of input data to be next entered. This is followed by the display state (c) after the passage of a given length of time (say, 0.5 sec), the display state (d) after the passage of further 0.5 sec and so forth. In this way, the display contents are shifted in the sequence of (b)→(c)→(d) . . . (e)→(f)→. . . (g)→(h)→(i) at every given length of time. After the overall display contents have gone, the display panel is restored to the initial or conventional state. The above operation sequence is then repeated.

FIG. 3 is a block diagram of one embodiment of a calculator equipped with the display device according to the present invention. The embodiment shown in FIG. 3 contains a key input unit 3, a central processor unit 4 (hereinafter referred to as "CPU") described below for decoding and executing instructions, a character generator CRG 5 for decoding output signals from registeres SA and SX, a dot matrix type liquid display panel 6 of for example an eight digit capacity each digit in a 5×7 matrix, digit select signal leads 7 and segment select signal leads 8.

FIG. 4, a composite diagram of FIGS. 4A-4D, shows a logic wiring diagram of a specific example of the CPU scheme in the calculator whereby the display operation of the present invention is effected. FIG. 5 shows how to combine FIGS. 4A-4D concerning the CPU. The following will set forth a logic structure of the CPU.

[CPU ARCHITECTURE]

A random access memory RAM has a 4 bit input and output capacity and is accessible by a specific digit position thereof as identified by a digit address and a file address. The RAM includes a digit address counter BL, a digit address decoder DC₁, a file address counter BM, a file address decoder DC₂ and an adder AD₁ which serves as an adder and a subtractor respectively in the absence and presence of a control instruction 14 . It further includes a second adder AD₂ and a gate G₁ for providing either a digit "1" or an operand I_(A) to an input to the adder/subtractor AD₁ and delivering I or I_(A) when a control instruction 15 or 16 is developed, respectively. An input gate G₂ is provided for the memory digit address counter BL, which enables the output of the adder/subtractor AD₁, the operand I_(A) and another operand I_(B) to pass therethrough respectively when control instructions 10 , 11 and 12 are developed. A gate G₃ is disposed to provide a digit "1" or the operand I_(A) to an input to the adder/subtractor, the former being provided upon the development of an instruction 5 and the latter upon the development of an instruction 6 . A gate G₄ is an input gate to the memory file address BM which enables the output of the adder AD₂, the operand I_(A) and the contents of an accumulator ACC to pass upon the development of instructions 7 , 8 and 9 . A file selection gate G₅ is further provided for the memory RAM. A decoder DC₃ translates the operand I_(A) and supplies a gate G₆ with a desired bit specifying signal. The gate G₆ contains a circuit arrangement for introducing a binary code "1" into a specific bit position of the memory identified by the operand decoder DC₃ and a binary code "D" into a specific bit position identified by DC₃, respectively, when a control instruction 2 or 3 is developed. Upon the development of an instruction 4 the contents of the accumulator ACC are read out.

A read only memory ROM has its associated program counter PL which specifies a desired step in the read only memory ROM. The read only memory ROM further contains a step access decoder DC₄ and an output gate G₇ which shuts off transmission of the output of the ROM to an instruction decoder DC₅ when a judge flip flop F/F J is set. The instruction decoder DC₅ is adapted to decode instruction codes derived from the ROM and divide them into an operation code area I_(O) and operand areas I_(A) and I_(B), the operation code being decoded into any control instruction 1 - 61 . The decoder DC₅ is further adapted to output the operand I_(A) or I_(B) as it is when sensing an operation code accompanied by an operand. An adder AD₃ increments the contents of the program counter PL. An input gate G₈ associated with the program counter PL provides the operand I_(A) and transmits the contents of a program stack register SP when the instructions 20 and 61 are developed, respectively. When the instructions 20 , 61 and 60 are being processed, any output of the adder AD₃ is not transmitted. Otherwise the AD₃ output is transmitted to automatically load "1" into the contents of the program counter PL. A flag flip flop FC has an input gate G₉ therefor which introduces binary codes "1" and "0" into the flag flip flop FC when the instructions 17 and 18 are developed, respectively. A key signal generating gate G₁₀ provides the output of the memory digit address decoder DC₁ without any change when the flag F/F FC is in the reset state (0), and renders all outputs I₁ -I_(n) "1" whatever output DC₁ provides when FC is in the set state (1). The accumulator ACC is 4 bits long and a temporary register X is also 4 bits long. An input gate G₁₁ for the temporary register X transmits the contents of the accumulator ACC and the stack register SX respectively upon the development of the instructions 29 and 59 . An adder AD₄ executes a binary addition on the contents of the accumulator ACC and other data. The output C₄ of the adder AD₄ assumes "1" when the fourth bit binary addition yields a carry. A carry F/F C has its associated input gate G₁₂ which sets "1" into the carry F/F C in the presence of "1" of the fourth bit carry C₄ and "0" into the same in the absence of C₄ (0). "1" and "0" are set into C upon the development of 21 and 22 , respectively. A carry (C) input gate G₁₈ enables the adder AD₄ to perform binary additions with a carry and thus transmits the output of the carry F/F C into the adder AD₄ in response to the instruction 25 . An input gate G₁₄ is provided for the adder AD₄ and transfers the output of the memory RAM and the operand I_(A) upon the development of 23 and 24 , respectively. An output buffer register F has a 4 bit capacity and an input gate which enables the contents of the accumulator ACC to enter into F upon the development of 31 . An output decoder SD decodes the contents of the output buffer F into display segment signals SS₁ -SS_(n). An output buffer register W has a shift circuit SHC which shifts the overall bit contents of the output buffer register W one bit to the right at a time in response to 32 or 33 . An input gate G₁₆ for the output buffer register W provides "1" and "0" to the first bit position of W upon 32 and 33 , respectively. Immediately before 37 1" or or "0" enters into the first bit position of W the output buffer shift circuit SHC becomes operative.

An output control flag F/F N_(p) has an input gate G₁₇ for receiving "1" and "0" upon the development of 34 and 35 , respectively.

The buffer register W is provided with an output control gate G₁₈ for providing the respective bit outputs thereof at one time only when the flag F/F N_(p) is in the set state (1). There are further provided a judge F/F J, inverters IV₁ -IV₄ and an input gate G₁₉ for the judge F/F J for transferring the state of an input KN₁ l into J upon the development of 36 . In the case where KN₁ =0, J=1 because of intervention of the inverter IV₁. An input gate G₂₀ for the judge F/F J is adapted to transfer the state of an input KN₂ into J upon 38 . When KF₁ =0, J=1 becuase of intervention of the inverter IV₃. An input gate G₂₂ for the judge F/F J is adapted to transfer the state of the input KF₂ into J upon 39 . When KF₂ =0, J=1 because of the intervened inverter IV.sub. 4. An input gate G₂₃ is provided for the judge flip flop J for transmission of the state of an input AK into J upon the development of 40 . When AK=1, J=1. An input gate G₂₄ is provided for the judge flip flop J to transmit the state of an input TAB into J pursuant to 41 . When TAB=1, J=1. A gate G₂₅ is provided for setting the judge F/F J upon the development of 42 . A comparator V₁ compares the contents of the memory digit address counter BL with preselected data and provides an output "1" if there is agreement. The comparator V₁ becomes operative when 43 or 44 is developed. The data to be compared are derived from a gate G₂₆ which is an input gate to the comparator V₁. The data n₁ to be compared are a specific higher address value which is often available in controlling the RAM. n₁ and n₂ are provided for comparison purposes upon the development of 43 and 44 , respectively.

An input gate G₂₇ is provided for the decision F/F J to enter "1" into J when the carry F/F C assumes "1" upon the development of 45 .

A decoder DC₆ decodes the operand I_(A) and helps decisions as to whether or not the contents of a desired bit position of the RAM are "1". A gate G₂₈ transfers the contents of the RAM as specified by the operand decoder DC₆ into the judge F/F when 46 is derived. When the specified bit position of the RAM assumes "1", J=1. A comparator V₂ decides whether or not the contents of the accumulator ACC are equal to the operand I_(A) and provides an output "1" when the affirmative answer is provided. The comparator V₂ becomes operative according to 47 . A comparator V₃ decides under 48 whether the contents of the memory digit address counter BL are equal to the operand I_(A) and provides an output "1" when the affirmative answer is obtained. A comparator V₄ decides whether the contents of the accumulator ACC agree with the contents of the RAM and provides an output "1" in the presence of the agreement. A gate G₂₉ transfers the fourth bit carry C₄ occurring during additions into the judge F/F J. Upon the development of 50 C₄ is sent to F/F J. J=1 in the presence of C₄. A flag flip flop FA has an input gate G₃₁ which provides outputs "1" and "0" upon the development of 52 and 53 , respectively. An input gate G₃₂ is provided for setting the judge F/F J when the flag flip flop FA assumes "1". A flag flip flop F_(B) also has an input gate G₃₃ which provides outputs "1" and "0" upon 55 and 56 , respectively. An input gate G₃₄ for the judge flip flop J is adapted to transfer the contents of the flag flip flop F_(B) into the F/F J upon the development of 54 . An input gate G₃₅ associated with the judge F/F J is provided for transmission of the contents of an input B upon 19 . When B=1, J=1. An input gate G₃₆ associated with the accumulator ACC is provided for transferring the output of the adder AD₄ upon 26 and transferring the contents of the accumulator ACC after inverted via an inverter IV₅ upon 27 . The contents of the memory RAM are transferred upon 28 , the operand I_(A) upon 13 , the 4 bit input contents k₁ -k₄ upon 57 , and the contents of the stack register SA upon 59 . A stack register SA provides the output outside the present system. A stack register SX also provides the output outside the system. An input gate G₃₇ associated with the stack register SA transfers the accumulator ACC upon 58 . An input gate G₃₈ associated with the stack register SX transfers the contents of the temporary register X. A program stack register SP has an input gate G₃₉ for loading the contents of the program counter PL incremented by "1" through the adder into the program stack register.

An illustrative example of the instruction codes contained within the ROM of the CPU structure, the name and function of the instruction codes and the control instructions developed pursuant to the instruction codes will now be tabulated in Table 1 wherein A: the instruction codes, B: the instruction name, C: the instruction description and D: The CPU control instructions.

                  TABLE 1                                                          ______________________________________                                         A            B         D                                                       ______________________________________                                         1      I.sub.O   SKIP      ○42                                          2      I.sub.O   AD        ○23, ○26                              3      I.sub.O   ADC       ○23, ○26, ○25, ○1       4      I.sub.O   ADCSK     ○23, ○26, ○25,                                            ○50, ○1                               5      I.sub.O I.sub.A                                                                              ADI     ○24, ○26, ○50                6      I.sub.O I.sub.A                                                                              DC      ○24, ○26, ○50                7      I.sub.O   SC        ○21                                          8      I.sub.O   RC        ○22                                          9      I.sub.O I.sub.A                                                                              SM      ○2                                         10     I.sub.O I.sub.A                                                                              RM      ○3                                         11     I.sub.O   COMA      ○27                                          12     I.sub.O I.sub.A                                                                              LDI     ○13                                        13     I.sub.O I.sub.A                                                                              L       ○28, ○8                             14     I.sub.O I.sub.A                                                                              LI      ○28, ○8, ○15,                                             ○10, ○43                            15     I.sub.O I.sub.A                                                                              XD      ○28, ○8, ○14,                                             ○15, ○10, ○44                16     I.sub.O I.sub.A                                                                              X       ○28, ○4, ○8                  17     I.sub.O I.sub.A                                                                              XI      ○28, ○4, ○8,                                              ○15, ○10, ○43                18     I.sub.O I.sub.A                                                                              XD      ○28, ○4, ○8,                                              ○14, ○16, ○10,                                            ○44                                        19     I.sub.O I.sub.A                                                                              LBLI    ○11                                        20     I.sub.O                                                                              I.sub.A                                                                              I.sub.B                                                                            LB      ○8, ○12                           21     I.sub.O I.sub.A                                                                              ABLI    ○16, ○10, ○43                22     I.sub.O I.sub.A                                                                              ABMI    ○6, ○7                              23     I.sub.O I.sub.A                                                                              T       ○20                                        24     I.sub.O   SKC       ○45                                          25     I.sub.O I.sub.A                                                                              SKM     ○46                                        26     I.sub.O I.sub.A                                                                              SKBI    ○48                                        27     I.sub.O I.sub.A                                                                              SKAI    ○47                                        28     I.sub.O   SKAM      ○49                                          29     I.sub.O   SKN.sub.1 ○36                                          30     I.sub.O   SKN.sub.2 ○37                                          31     I.sub.O   SKF.sub.1 ○38                                          32     I.sub.O   SKF.sub.2 ○39                                          33     I.sub.O   SKAK      ○40                                          34     I.sub.O   SKTAB     ○41                                          35     I.sub.O   SKFA      ○51                                          36     I.sub.O   SKFB      ○54                                          37     I.sub.O   WIS       ○32                                          38     I.sub.O   WIR       ○33                                          39     I.sub.O   NPS       ○34                                          40     I.sub.O   NPR       ○35                                          41     I.sub.O   ATF       ○31                                          42     I.sub.O   LXA       ○29                                          43     I.sub.O   XAX       ○29, ○30                              44     I.sub.O   SFA       ○52                                          45     I.sub.O   RFA       ○53                                          46     I.sub.O   SFB       ○55                                          47     I.sub.O   RFB       ○56                                          48     I.sub.O   SFC       17                                                  49     I.sub.O   RFC       18                                                  50     I.sub.O   SKB       19                                                  51     I.sub.O   KTA       57                                                  52     I.sub.O   STPO      58                                                  53     I.sub.O   EXPO      58, 59                                              54     I.sub.O I.sub.A                                                                              TML     62, 20                                            55     I.sub.O   RIT       61                                                  ______________________________________                                    

Instruction Description (C)

(1) SKIP

Only the program counter PL is incremented without executing a next program step instruction, thus skipping a program step

(2) AD

A binary addition is effected on the contents of the accumulator ACC and the contents of the RAM, the addition results being loaded back into the accumulator ACC.

(3) ADC

A binary addition is effected on the contents of the accumulator ACC, the memory RAM and the carry F/F C, the results being loaded back to the accumulator ACC.

(4) ADCSK

A binary addition is effected on the contents of the accumulator ACC, the memory RAM and the carry flip flop C, the results being loaded into the accumulator ACC. If the fourth bit carry C₄ occurs in the results, then a next program step is skipped.

(5) ADI

A binary addition is achieved upon the contents of the accumulator ACC and the operand I_(A) and the results are loaded into the accumulator ACC. If the fourth bit carry C₄ is developed in the addition results, then a next program step is skipped.

(6) DC

The operand I_(A) is fixed as "1010" (a decimal number "10") and a binary addition is effected on the contents of the accumulator ACC and the operand I_(A) in the same way as in the ADI instruction. The decimal number 10 is added to the contents of the accumulator ACC, the results of the addition being loaded into ACC.

(7) SC

The carry F/F C is set ("1" enters into C).

(8) RC

The carry F/F C is reset ("0" enters into C).

(9) SM

The contents of the operand I_(A) are decoded to give access to a desired bit position of the memroy specified by the operand ("1" enters).

(10) RM

The contents of the operand I_(A) are interpreted to reset a desired bit position of the memory specified by the operand ("0" enters).

(11) COMA

The respective bits of the accumulator ACC are inverted and the resulting complement to "15" is introduced into ACC.

(12) LDI

The operand I_(A) enters into the accumulator ACC.

(13) L

The contents of the memory RAM are sent to the accumulator ACC and the operand I_(A) to the file address counter BM.

(14) LI

The contents of the memory RAM are sent to the accumulator ACC and the operand I_(A) to the memory file address counter BM. At this time the memory digit address counter BL is incremented. If the contents of BL agree with the preselected value n₁, then a next program step is skipped.

(15) XD

The contents of the memory RAM are exchanged with the contents of ACC and the operand I_(A) is sent to the memory file address counter BM. The memory digit address counter BL is decremented. In the event that the contents of BL agree with the preselected value n₂, then a next program step is skipped.

(16) X

The contents of the memory RAM are exchanged with the contents of the accumulator ACC and the operand I_(A) is loaded into the memory file address counter BM.

(17) XI

The contents of the memory RAM are exchanged with the contents of the accumulator ACC and the operand I_(A) is sent to the memory file address counter BM. The memory digit address counter BL is incremented. In the event that BL is equal to the preselected value n₁, a next program step is skipped.

(18) XD

The contents of the memory RAM replaces the contents of the accumulator ACC, the operand I_(A) being sent to the memory file address counter BM. The memory digit address counter BL at this time is incremented. If the contents of BL are equal to n₂, then a next program step is skipped.

(19) LBLI

The operand I_(A) is loaded into the memory digit address counter BL.

(20) LB

The operand I_(A) is loaded into the memory file address counter BM and the operand B to the memory digit address counter BL.

(21) ABLI

The operand I_(A) is added to the contents of the memory digit address counter BL in a binary addition fashion, the results being loaded back to BL. If the contents of BL are equal to n₁, then no next program step is carried out.

(22) ABMI

The operand I_(A) is added to the contents of the memory file address counter BM in a binary fashion, the results being into BM.

(23) T

The operand I_(A) is loaded into the program step counter PL.

(24) SKC

If the carry flip flop C is "1", then no next program step is taken.

(25) SKM

The contents of the operand I_(A) are decoded and a next program step is skipped as long as a specific bit position of the memory specified by the operand I_(A) assumes "1".

(26) SKBI

The contents of the memory digit address counter BL are compared with the operand I_(A) and a next succeeding program step is skipped when there is agreement.

(27) SKAI

The contens of the accumulator ACC are compared with the operand I_(A) and if both are equal to each other a next program step is skipped.

(28) SKAM

The contents of the accumulator ACC are compared with the contents of the RAM and if both are equal a next program step is skipped.

(29) SKN₁

When the input KN₁ is "0", a next program step is skipped.

(30) SKN₂

When the input KN₂ is "0", a next program step is skipped.

(31) SKF₁

When the input KF₁ is "0", a next program step is skipped.

(32) SKF₂

When the input KF₂ is "0", a next program step is skipped.

(33) SKAK

When the input AK is "1", a next program step is skipped.

(34) SKTAB

When the input TAB is "1", a next program step is skipped.

(35) SKFA

When the flag flip flop F/A assumes "1" a next program step is skipped.

(36) SKFB

When the flag flip flop F_(B) assumes "1", a next program step is skipped.

(37) WIS

The contents of the output buffer register W are one bit right shifted, the first bit position (the most significant bit position) receiving "1".

(38) WIR

The contents of the output buffer register W are one bit right shifted, the first bit position (the most significant bit position being loaded with "0".

(39) NPS

The output control F/F N_(p) for the buffer register W is set ("1" enters).

(40) NPR

The buffer register output control flip flop N_(p) is reset ("0" enters therein).

(41) ATF

The contents of the accumulator ACC are transferred into the output buffer register F.

(42) LXA

The contents of the accumulator ACC are unloaded into the temporary register X.

(43) XAX

The contents of the accumulator ACC are exchanged with the contents of the temporary register X.

(44) SFA

The flag F/F FA is set (an input of "1").

(45) RFA

The flag F/F FA is reset (an input of "0").

(46) SFB

The flag flip flop F_(B) is set (an input of "1").

(47) RFB

The flag flip flop F_(B) is reset (an input of "0").

(48) SFC

An input testing flag F/F F_(C) is set (an input of "1").

(49) RFC

The input testing flag F/F F_(C) is reset (an input of "0").

(50) SKB

When an input β is "1", a next program step is skipped.

(51) KTA

The inputs k₁ -k₄ are introduced into the accumulator ACC.

(52) STPO

The contents of the accumulator ACC are sent to the stack register SA and the contents of the temporary register X to the stack register SX.

(53) EXPO

The contents of the accumulator ACC are exchanged with the stack register SA and the contents of the temporary register X with the stack register SX.

(54) TML

The contents of the program counter P_(L) incremented by one are transferred into the program stack register SP and the operand I_(A) into the program counter P_(L).

(55) RIT

The contents of the program stack register SP are transmitted into the program counter P_(L).

Table 2 sets forth the relationship between the operation codes contained within the ROM of the CPU structure and the operand.

                  TABLE 2                                                          ______________________________________                                          ##STR1##                                                                       ##STR2##                                                                      ______________________________________                                          wherein I.sub.O : the operation codes and                                      I.sub.A, I.sub.B : the operands                                          

Taking an example wherein the output of the read only memory ROM is 10 bit long, the instructoin decoder DC₅ decides whether the instruction AD or COMA (see TAble 1) assumes "0001011000" or "0001011111" and develops the control instructions 23 , 26 , or 27 . SKBI is identified by the fact that the upper six bits assume "000110", the lower 4 bits "0010" being treated as the operand I_(A) and the remaining ninth and tenth bits "11" as the operand I_(B). The operand forms part of instruction words and specifies data and addresses for next succeeding instructions and can be called an address area of an instruction.

Major processing operations (a processing list) of the CPU structure will now be described in sufficient detail.

[PROCESSING LIST]

(I) A same numeral N is loaded into a specific region of the memory RAM (NNN→X)

(II) A predetermined number of different numerals are loaded into a specific region of the memory (N₁, N₂, N₃, . . . →X)

(III) The contents of a specific region of the memory are transferred into a different region of the memory (X→Y)

(IV) The contents of a specific region of the memory are exchanged with that of a different region (X⊖Y)

(V) A given numeral N is added or subtracted in a binary fashion from the contents of a specific region of the memory (X±N)

(VI) The contents of a specific region of the memory are added in a decimal fashion to the contents of a different region (X±Y)

(VII) The contents of a specific region of the memory are one digit shifted (X right, X left)

(VIII) A one bit conditional F/F associated with a specific region of the memory is set or reset (F set, F reset)

(IX) The state of the one bit conditional F/F associated with a specific region of the memory is sensed and a next succeeding program address is changed according to the results of the state detection.

(X) It is decided whether the digit contents of a specific region of the memory reach a preselected numeral and a next succeeding program step is altered according to the results of such decision.

(IX) It is decided whether the plural digit contents of a specific region of the memory are equal to a preselected numeral and a program step is altered according to the results of the decision.

(XII) It is decided whether the digit contents of a specific region of the memory are smaller than a given value and a program step to be next executed is changed according to the decision.

(XIII) It is decided whether the contents of a specific region of the memory are greater than a given value and the results of such decision alter a program step to be next executed.

(XIV) The contents of a specific region of the memory are displayed. (XV) What kind of a key switch is actuated is decided.

The above processing events in (1)-(15) above are executed according to the instruction codes step by step in the following manner.

    ______________________________________                                         (I) PROCEDURE OF LOADING A SAME VALUE N INTO A                                 SPECIFIC REGION OF THE MEMORY (NNN→X)                                   (Type 1)                                                                        ##STR3##                                                                      P.sub.1 .....                                                                          The first digit position of the memory                                         to be processed is specified by a file                                         address m.sub.A and a digit address n.sub.E.                           P.sub.2 .....                                                                          The value N is loaded into ACC.                                        P.sub.3 .....                                                                          The value N is loaded into the specified                                       region of the memory by exchange between                                       the memory and ACC. With no change                                             in the file address of the memory,                                             m.sub.A is specified and the digit address                                     is decremented to determine a digit to                                         be next introduced. By determing n.sub.2                                       as the final digit value n.sub.A to be                                         introduced, the next step P.sub.4 is skipped                                   to complete the processing of the Type                                         1 since BL = n.sub.2 under the condition                                       that the value N has been completely load-                                     ed into the specific region.                                           P.sub.4 .....                                                                          LDI and XD are carried out repeatedly                                          from the program address P.sub.2 up to BL = V.                         (Type 2)                                                                        ##STR4##                                                                      P.sub.1 .....                                                                          The digit of the memory to be processed                                        is determined by the file address m.sub.B                                      and the digit address n.sub.C.                                         P.sub.2 .....                                                                          The ACC is loaded with the value N.                                    P.sub.3 .....                                                                          By exchange between the memory and ACC                                         the value N is loaded into the above                                           specified region of the memory. This                                           completes the processing of Type 2.                                            An operand area of X.sub.D is necessary to                                     the next succeeding process and not to                                         this step.                                                             (Type 3)                                                                        ##STR5##                                                                      P.sub.1 .....                                                                          The first digit of the memory to be                                            processed is specified by the file                                             address m.sub.C and the digit address n.sub.O.                         P.sub.2 .....                                                                          The ACC is loaded with the value N.                                    P.sub.3 .....                                                                          By exchange between the memory and ACC                                         the value N is loaded into that specified                                      region of the memory. With no change in                                        the file address of the memory m.sub.C is                                      specified and the digit address is decrement-                                  ed in order to determine the digit to be                                       next loaded therein.                                                   P.sub.4 .....                                                                          It is decided whether the digit processed                                      during the step P.sub.3 is the final digit n.sub.B.                            If it is n.sub.B, then the digit address is                                    decremented to n.sub.A. An operand area of                                     the SKI instruction is occupied by n.sub.A,                                    thus loading the final digit with the value                                    N. In reaching P.sub.4, conditions are fulfilled                               and the next step P.sub.5 is skipped, thereby                                  terminating the type 3. If the condi-                                          tions are not fulfilled, P.sub.5 is then                                       reached.                                                               P.sub.5 .....                                                                          The program address P.sub.2 is specified and                                   P.sub.2 -P.sub.4 are repeated until BL = n.sub.A .                     (II) PROCEDURE OF LOADING A PREDETERMINED                                      NUMBER OF DIFFERENT VALUES INTO A SPECIFIC                                     REGION OF THE MEMORY (N.sub.1, N.sub.2, N.sub.3, .....→X)               (Type 1) For example, four digit values N.sub.4 N.sub.3 N.sub.2 N.sub.1        are                                                                            loaded an arbitraray digit position in the same manner                         as above.                                                                       ##STR6##                                                                      P.sub.1 .....                                                                          The first processed digit position of                                          the memory is specified by the file address                                    m.sub.A and the digit address n.sub.E.                                 P.sub.2 .....                                                                          A constant N.sub.1 is loaded into ACC.                                 P.sub.3 .....                                                                          Through exchange between the memory and                                        the ACC the value N.sub.1 is loaded into the                                   above specified region of the memory.                                          The file address of the memory remains                                         unchanged as m.sub.A, whereas the digit                                        address is up for introduction of the                                          next digit.                                                            P.sub.4 .....                                                                          A second constant N.sub.2 is loaded into ACC.                          P.sub.5 .....                                                                          Since the second digit of the memory                                           has been specified during P.sub.3, the second                                  constant N.sub.2 is loaded into the second                                     digit position of the memory through                                           exchange between the memory and ACC.                                   P.sub.6 -P.sub.9 ..                                                                    The same as in the above paragraph.                                    (Type 2)                                                                       Any value of 0-15 is loaded into a predetermined register.                      ##STR7##                                                                      P.sub.1 .....                                                                          The value N is loaded into ACC.                                        P.sub.2 .....                                                                          The value N is transmitted from ACC                                            into the register X.                                                   (III) PROCEDURE OF TRANSFERRING THE CONTENTS                                   OF A SPECIFIC REGION OF THE MEMORY TO A                                        DIFFERENT REGION OF THE MEMORY (X → Y)                                  (Type 1)                                                                        ##STR8##                                                                      P.sub.1 .....                                                                          The first memory file address is                                               specified as m.sub.A  and the first digit                                      address as n.sub.E.                                                    P.sub.2 .....                                                                          The contents of the first digit position                                       of the memory are loaded into ACC and                                          its designation, the second memory                                             file address is specified as m.sub.B prior                                     to the transmission step P.sub.3.                                      P.sub.3 .....                                                                          The first digit memory contents loaded                                         into the ACC are replaced by the same                                          second memory digit contents so that                                           the first memory contents are transmitted                                      into the second memory. In order to                                            repeat the above process, the first                                            memory file address m.sub.A is again set.                                      The value of the final digit n.sub.A to be                                     transmitted is previously selected to be                                       n.sub.1. Since BL → n.sub.1 after the overall                           first memory contents have been sent to                                        the second memory, the next step P.sub.4 is                                    skipped to complete the processing of Type                                     1. The digit address is progressively                                          incremented until BL = V (the final digit).                                    Through the step P.sub.4 the file address is                                   set up at m.sub.A to lead back to P.sub.2, thereby                             specifying the first memory.                                           P.sub.4 .....                                                                          The program address is set at the step P.sub.2                                 and the instructions P.sub.2 and P.sub.3 are                                   repeatedly executed until BL = n.sub.1. The                                    transmission step is advanced digit by                                         digit.                                                                 (Type 2)                                                                        ##STR9##                                                                      P.sub.1 .....                                                                          The region of the memory to be processed                                       is determined by the file address m.sub.A and                                  the digit address n.sub.C.                                             P.sub.2 .....                                                                          The contents of the memory as specified                                        above are unloaded into ACC and the                                            memory file address is set at m.sub.C prior                                    to the next transmission step P.sub.4.                                 P.sub.3 .....                                                                          The digit address of the memory, the                                           destination for the transmission process,                                      is specified as m.sub.C. The destinated region                                 of the memory is specified via the steps                                       P.sub.2 and P.sub.3.                                                   P.sub.4 .....                                                                          The contents of ACC are exchanged with                                         the contents of the regions of the                                             memory specified bu P.sub.2 and P.sub.3. The operand                           of X has no connection with the present                                        process.                                                               (Type 3)                                                                        ##STR10##                                                                     P.sub.1 .....                                                                          The region of the memory to be processed                                       is identified by the file address m.sub.A and                                  the digit address n.sub. C.                                            P.sub.2 .....                                                                          The contents of the memory region specified                                    during P.sub.1 are unloaded into ACC.                                  P.sub.3 .....                                                                          The contents of the memory transmitted                                         from ACC are sent to the register X, com-                                      pleting the type 3 processing.                                         (IV) PROCEDURE OF EXCHANGING CONTENTS                                          BETWEEN A SPECIFIC REGION OF THE MEMORY AND                                    A DIFFERENT REGION (X → Y)                                              (Type 1)                                                                        ##STR11##                                                                     P.sub.1 .....                                                                          The first memory file address to be                                            processed is specified as m.sub.A and the                                      first digit address as n.sub.E.                                        P.sub.2 The specific digit contents of the                                             first memory are loaded into ACC and                                           the second memory file address is                                              specified as m.sub.B for preparation of the                                    next step.                                                             P.sub.3 .....                                                                          The specific digit contents of the first                                       memory contained within ACC are exchanged                                      with the same digit contents of the                                            second memory specified by P.sub.2. The file                                   address of the first memory is specified                                       as m.sub.A in order to load the contents of                                    the memory now in ACC into the first                                           memory.                                                                P.sub.4 .....                                                                          The contents of the second memory now                                          in ACC are exchanged with the contents                                         of the first memory at the corresponding                                       digit positions so that the contents                                           of the second memory are transferred                                           to the first memory. Exchanges are                                             carried out during the steps P.sub.2 -P.sub.4.                                 The first memory is specified on by the                                        file address m.sub.A, while the digit address                                  is incremented to select a next address.                                       Exchange is carried out progressively                                          digit by digit. The final digit value n.sub.A                                  is previously set at n.sub.1 such that B.sub.L = n.sub.1                       after the exchange operation between                                           the first memory and the second has been                                       effected throughout the all digit posi-                                        tions, thus skipping the next step P.sub.5                                     and completing the processing of Type 1.                               P.sub.5 .....                                                                          The program address P.sub.2 is selected and                                    the instructions for P.sub.2 to P.sub.4 are executed                           repeatedly until B.sub.L = n.sub.1. The exchange                               operation is advanced digit by digit.                                  (Type 2)                                                                        ##STR12##                                                                     P.sub.1 .....                                                                          The file address of the first memory                                           to be processed is specified as m.sub.A and the                                digit address as n.sub.C.                                              P.sub.2 .....                                                                          The contents of the specific digit posi-                                       tion of the first memory are unloaded                                          into ACC and the file address of the                                           second memory is specified as m.sub.C and                                      ready to exchange.                                                     P.sub.3 .....                                                                          The digit address of the second memory,                                        the destination for the exchange process,                                      is specified as n.sub.O to determine the                                       destinated memory address.                                             P.sub.4 .....                                                                          The contents of the first memory now                                           within ACC are exchanged with that of the                                      second memory. At the same time the                                            file address m.sub.B of the first memory is                                    again specified to transfer the contents                                       of the first memory to the first memory.                               P.sub.5 .....                                                                          The digit address n.sub.C of the first memory                                  is specified to determine the destination                                      address of the first memory.                                           P.sub.6 .....                                                                          The contents of the second memory now                                          within ACC are exchanged with the contents                                     of the first memory.                                                   (Type 3)                                                                        ##STR13##                                                                     P.sub.1 .....                                                                          The file address m.sub.A of the first memory                                   to be processed is specified and the                                           digit address n.sub.C is specified.                                    P.sub.2 .....                                                                          The contents of the first memory are                                           loaded into ACC and the file address m.sub.C                                   of the second memory is selected.                                      P.sub.3 .....                                                                          The exchange is carried out between                                            the first and second memory so that                                            the contents of the first memory are                                           loaded into the second memory. Prior                                           to the step P.sub.4 the file address m.sub.B of                                the first memory is selected again.                                    P.sub.4 .....                                                                          The exchange is effected between the                                           contents of the second memory and the                                          first memory.                                                          (Type 4)                                                                        ##STR14##                                                                     P.sub.1 .....                                                                          The region of the memory to be                                                 processed is specified by the file                                             address m.sub.A and the digit address n.sub.C.                         P.sub.2 .....                                                                          The contents of the memory region                                              specified in P.sub.1 above are loaded into                                     ACC. The file address m.sub.B is kept being                                    selected prior to the exchange with the                                        contents of the register X.                                            P.sub. 3 .....                                                                         The exchange is effected between ACC                                           and the register X so that the contents                                        of the memory are shifted to the                                               register X.                                                            P.sub.4 .....                                                                          Through the exchange between ACC contain-                                      ing the contents of the register X and                                         the memory, the contents of the register                                       X are substantially transferred into the                                       memory, thus accomplishing the Type 4                                          processing.                                                            (V) PROCEDURE OF EFFECTING A BINARY ADDITION                                   OR SUBTRACTION OF A GIVEN VALUE N ONTO A                                       SPECIFIC REGION OF THE MEMORY                                                  (Type 1) M.sub.1 + N → M                                                 ##STR15##                                                                     P.sub.1 .....                                                                          The region of the memory to be processed                                       is specified by the file address m.sub.B and                                   the digit address n.sub.C.                                             P.sub.2 .....                                                                          The contents of the memory specified by                                        the step P.sub.1 are unloaded into ACC.                                        The memory file address is set again at                                        m.sub.B to specify the same memory.                                    P.sub.3 .....                                                                          The operand specifies the value N to                                           be added and the contents of the memory                                        contained within ACC are added with the                                        value N, the results being loaded back                                         to ACC.                                                                P.sub.4 .....                                                                          The sum contained with ACC is exchanged                                        with the contents of the memory specified                                      by the step P.sub.2, thus completing the Type                                  1 processing.                                                          (Type 2) X + N → X                                                       ##STR16##                                                                     P.sub.1 .....                                                                          The exchange is effected between the                                           register X and ACC.                                                    P.sub.2 .....                                                                          The operand specifies the value N to                                           be added and an addition is carried                                            out on the contents of the register                                            X now within ACC and the value N, with                                         the results back to ACC.                                               P.sub.3 .....                                                                          Through the exchange between the result-                                       ing sum within ACC and the contents of                                         the register X, the processing of Type                                         2 (X + N → X) is performed.                                     (Type 3) M.sub.1 + N → M.sub.2                                           ##STR17##                                                                     P.sub.1 .....                                                                          The region of the first memory to be                                           processed is decided by the file address                                       m.sub.B and the digit address n.sub.C.                                 P.sub.2 .....                                                                          The contents of the memory specified                                           by P.sub.1 are loaded into ACC. The file                                       address m.sub.C of the second memory is specified                              to return addition results to the second                                       memory.                                                                P.sub.3 .....                                                                          The operand specifies the value N to be                                        added and the value N is added to the                                          contents of the memory now within ACC,                                         with the results being loaded into ACC.                                P.sub.4 .....                                                                          The resulting sum within ACC is exchanged                                      with the contents of the second memory                                         as specified by P.sub.2, thus completing the                                   processing of Type 3.                                                  (Type 4) M.sub.1 - N → M.sub.1                                           ##STR18##                                                                     P.sub.1 .....                                                                          There are specified the file address m.sub.B                                   and the digit address n.sub.C of the memory                                    to be processed.                                                       P.sub.2 .....                                                                          Subtraction is carried out in such a                                           way that the complement of a subtrahend is                                     added to a minuend and the F/F C remains set                                   because of the absence of a borrow from                                        a lower digit position.                                                P.sub.3 .....                                                                          ACC is loaded with the subtrahend N.                                   P.sub.4 .....                                                                          The complement of the subtrahend to "15"                                       is evaluated and loaded into ACC.                                      P.sub.5 .....                                                                          In the event that any borrow occurs during                                     the subtraction, the complement of the                                         subtrahend to "16" is added to the                                             minuend. If a borrow free state is denoted                                     as C = 1, then a straight binary subtraction                                    ##STR19##                                                             P.sub.6 .....                                                                          The resulting difference during P.sub.5 is                                     returned to the same memory through the                                        exchange between ACC and that memory.                                  (Type 5) M.sub.1 - N → M.sub.2                                           ##STR20##                                                                     P.sub.6 .....                                                                          To load the resulting difference during                                        P.sub.5 into the second memory, the file                                       address m.sub.C and the digit address n.sub.C of the                           second memory are selected.                                            P.sub.7 .....                                                                          Through exchange the resulting difference                                      is transferred from ACC into the second                                        memory as specified by the step P.sub.6.                               (Type 6)                                                                        ##STR21##                                                                     P.sub.1 .....                                                                          The file address m.sub.B and the digit                                         address n.sub.C of the memory ready for the                                    step P.sub.5 are selected.                                             P.sub.2 .....                                                                          Subtraction is carried out in the manner                                       of adding the complement of a subtrahend                                       to a minuend and the F/F C remains set                                         because of the absence of a borrow from                                        a lower digit position.                                                P.sub.3 .....                                                                          ACC is loaded with the subtrahend N.                                   P.sub.4 .....                                                                          The complement of the subtrahend to "15"                                       is evaluated and loaded into ACC.                                      P.sub.5 .....                                                                          To accomplish calculations with the contents                                   of the register X, the memory as specified                                     by P.sub.1 is loaded with the contents of ACC.                         P.sub.6 .....                                                                          The contents of the register X are                                             transmitted into ACC through the exchange                                      process. After this step the memory                                            contains the complement of the subtrahend                                      to "15" and ACC contains the contents of                                       X.                                                                     P.sub.7 .....                                                                          ACC + M + C corresponds to X - N and the                                       results of a binary subtraction are loaded                                     into ACC.                                                              P.sub.8 .....                                                                          The contents of ACC are exchanged with the                                     contents of X and the value of X - N is                                        transmitted into X, thereby completing the                                     processing of Type 6.                                                  (Type 7) N - M.sub.1 → M.sub.1                                           ##STR22##                                                                     P.sub.1 .....                                                                          The file address m.sub.B and the digit address                                 n.sub.C of the memory to be processed are                                      selected.                                                              P.sub.2 .....                                                                          One-digit subtraction is effected in the                                       manner of adding the complement of a                                           subtrahend to a minuend, in which case F/F C                                   remains set.                                                           P.sub.3 .....                                                                          ACC is loaded with a minuend.                                          P.sub.4 .....                                                                          The exchange is effected between the memory                                    (the subtrahend) and ACC and the memory file                                   address remains as m.sub.B for preparation of                                  P.sub.7.                                                               P.sub.5 .....                                                                          The complement of a subtrahend in ACC                                          to "15" is evaluated and loaded into ACC.                              P.sub.6 .....                                                                          In the event that there is no borrow from                                      a lower digit position, the complement of                                      a subtrahend to "16" is added to a                                             minuend. If a borrowless state is denoted                                      as C = 1, then N - M is substantially executed                                  ##STR23##                                                                     being loaded into ACC.                                                 P.sub.7 .....                                                                          Since the memory file address remains unchang-                                 ed during P.sub.4, the difference is unloaded                                  from ACC back to the memory, thus complet-                                     ing the proceesing of Type 7.                                          (Type 8) N - M.sub.1 → M.sub.2                                           ##STR24##                                                                     P.sub.1 .....                                                                          The file address m.sub.B and the digit address                                 n.sub.C of the memory to be processed are                                      selected.                                                              P.sub.2 .....                                                                          The contents specified by the step P.sub.1 and                                 corresponding to a subtrahend are loaded                                       into ACC. The file address m.sub.C of the second                               memory is specified for preparation of                                         a step P.sub.5.                                                        P.sub.3 .....                                                                          The complement of the subtrahend to "15"                                       is evaluated and loaded into ACC.                                      P.sub.4 .....                                                                          The operand is made a minuend plug "1".                                        This subtraction is one digit long and                                         accomplished by adding the complement of                                       the subtrahend to the minuend. A conven-                                       tional complementary addition is defined                                        ##STR25##                                                                     in the absence of a borrow as defined                                          by C = 1. Since the ADI instruction carries                                     ##STR26##                                                                     completes the processing of Type 8 of N - M,                                   the results being stored within ACC.                                   P.sub.5 .....                                                                          The difference obtained from the step P.sub.4                                  is transmitted into the second memory                                          specified by P.sub.2.                                                  (Type 9) M ± 1 → M                                                    ##STR27##                                                                     P.sub.1 .....                                                                          (When M + 1) ACC is loaded with a binary                                       number "0001" (=1).                                                    P.sub.1' .....                                                                         (When M - 1) ACC is loaded with a binary                                       number "1111" (=15).                                                   P.sub.2 .....                                                                          The file address m.sub.B and the digit address                                 n.sub.C of the memory to be processed are                                      selected.                                                              P.sub.3 .....                                                                          The contents of the memory specified by                                        P.sub.2 are added to the contents contained within                             ACC during P.sub.1 or P.sub.1 ', the sum thereof being                         loaded into ACC. In the case of P.sub.1 ACC + 1                                and in the case of P.sub.1 ' ACC - 1.                                  P.sub.4 .....                                                                          The results are unloaded from ACC to the                                       original memory position, thus completing the                                  processing fashion of Type 9.                                          (VI) PROCEDURE OF EFFECTING A DECIMAL                                          ADDITION OR SUBTRACTION BETWEEN A SPECIFIC                                     REGION OF THE MEMORY AND A DIFFERENT REGION                                    (Type 1) X + W → X                                                       ##STR28##                                                                     P.sub.1 .....                                                                          The first digit position of the first                                          memory to be processed is identified by                                        the file address m.sub.A and the digit address                                 n.sub.E.                                                               P.sub.2 .....                                                                          The carry F/F C is reset because of                                            a carry from a lower digit position in                                         effecting a first digit addition.                                      P.sub.3 .....                                                                          The contents of the specific digit position                                    of the first memory are loaded into ACC                                        and the file address m.sub.B of the second                                     memory is selected in advance of additions                                     with the contents of the second memory                                         during P.sub.4.                                                        P.sub.4 .....                                                                          "6" is added to the contents of the specific                                   digit position of the first memory now                                         loaded into ACC for the next succeeding                                        step P.sub.5 wherein a decimal carry is sensed                                 during addition.                                                       P.sub.5 .....                                                                          ACC already receives the contents of the                                       first memory compensated with "6" and a                                        straight binary addition is effected                                           upon the contents of ACC and the contents                                      of the second memory at the corresponding                                      digit positions, the results being loaded                                      back to ACC. In the event a carry is                                           developed during the binary addition at                                        the fourth bit position, P.sub.7 is reached                                    without passing P.sub.6. The presence of the                                   carry during the fourth bit addition implies                                   the development of a decimal carry.                                    P.sub.6 .....                                                                          In the event the decimal carry failed                                          to develop during the addition P.sub.5, "6"                                    for the process P.sub.4 is overruded. An                                       addition of "10" is same as a subtraction                                      of "6".                                                                P.sub.7 .....                                                                          The one-digit decimal sum is unloaded from                                     ACC into the second memory and the digit                                       address is incremented for a next digit                                        addition and the file address m.sub.A of the                                   first memory is selected. The final digit                                      to be added is previously set at n.sub.1. Since                                BL = n.sub.1 after the overall digit addition                                  is effected upon the first and second                                          memory, the next succeeding step P.sub.8 is                                    skipped to thereby complete the processing                                     of Type 1.                                                             P.sub.8 .....                                                                          The program address P.sub.3 is selected and the                                instructions P.sub.3 -P.sub.7 are repeatedly                                   executed until BL = n.sub.1. A decimal addition                                is effected digit by digit.                                            (Type 2) X - W → X                                                       ##STR29##                                                                     P.sub.1 .....                                                                          The first digit position of the first                                          memory to be processed is specified by                                         the file address m.sub.A and the digit address                                 n.sub.E.                                                               P.sub.2 .....                                                                          Subtraction is performed in the manner                                         of adding the complement of a subtrahend                                       to a minuend and F/F C is set because of                                       the absence of a borrow from a lower digit                                     position during the first digit subtraction.                           P.sub.3 .....                                                                          The contents of the specific digits in                                         the first memory, the subtrahend, are loaded                                   into ACC and the file address m.sub.B of the                                   second memory is specified in advance of                                       the step P.sub.7 with the second memory.                               P.sub.4 .....                                                                          The complement of the subtrahend to "15"                                       is evaluated and loaded into ACC.                                      P.sub.5 .....                                                                          In the event that there is no borrow from                                      a lower digit place, the complement of                                         the subtrahend is added to the minuend to                                      perform a subtraction. On the contrary,                                        in the presence of a borrow, the complement                                    of the subtrahend is added to the minuend.                                     If a borrowless state is denoted as C = 1,                                      ##STR30##                                                                     is effected. The development of a carry,                                       as a consequence of the execution of the                                       ADSCK instruction, implies failure to give                                     rise to a borrow and leads to the step P.sub.7                                 without the intervention of the step P.sub.6.                                  Under these circumstances the addition                                         is executed with the secondary memory, thus                                    executing substantially subtraction between                                    the first and second memories.                                         P.sub.6 .....                                                                          In the case where no carry is developed                                        during the execution of the ADCSK instruction                                  by the step P.sub.5, the calculation results are                               of the sexadecimal notation and thus                                           converted into a decimal code by                                               subtraction of "6" (equal to addition of                                       "10").                                                                 P.sub.7 .....                                                                          The resulting difference between the first                                     and second memories is transmitted from                                        ACC into the second memory. The digit                                          address is incremented and the file                                            address m.sub.A of the first memory is                                         specified in advance of a next succeeding                                      digit subtraction. The final digit to                                          be subtracted is previously determined                                         as n.sub.1. Since BL = n.sub.1 after the overall-                              digit subtraction has been completed, the                                      next step P.sub.8 is skipped to thereby conclude                               the processing of Type 2.                                              P.sub.8 .....                                                                          After selection of the program address P.sub.3                                 the instructions P.sub.3 -P.sub.7 are repeatedly                               executed until BL = n.sub.1.The decimal sub-                                   traction is advanced digit by digit.                                   (VII) PROCEDURE OF SHIFTING ONE DIGIT THE                                      CONTENTS OF A SPECIFIC REGION OF THE MEMORY                                    (Type 1) Right Shift                                                            ##STR31##                                                                     P.sub.1 .....                                                                          The file address m.sub.A and the digit address                                 n.sub.A of the memory to be processed are                                      determined.                                                            P.sub.2 .....                                                                          ACC is loaded with "0" and ready to                                            introduce "0" into the most significant                                        digit position when the right shift                                            operation is effected.                                                 P.sub.3 .....                                                                          The exchange is carried out between XCC                                        and the memory and the digit address is                                        decremented to specific a one digit lower                                      position. The memory address is still at                                       m.sub.A. XD is repeated executed through P.sub.4 and P.sub.3.                   ##STR32##                                                                     tted from ACC to the most significant digit                                    position of the memory which in turn provides                                  its original contents for ACC. When the                                        digit address is down via B and XD is about                                    to be executed at P.sub.3 via P.sub.4, the second most                         significant digit is selected to contain                                       the original content of the most signifi-                                      cant digit position which has previously                                       been contained within ACC. At this time                                        ACC is allowed to contain the contents of                                      the second most significant digit position.                                    The least significant digit is previously                                      selected as n.sub.2. If the transmission step                                  reaches the least significant digit position                                   BL = n.sub.2 is satisfied and P.sub.4 is skipped.                              In other words, the digit contents are shifted                                 down to thereby conclude the processing                                        of Type 1.                                                             P.sub.4 .....                                                                          XD is repeated at P.sub.3  until BL = V.                               (Type 2) Left Shift                                                             ##STR33##                                                                     P.sub.1 .....                                                                          The file address m.sub.A and the least signifi-                                cant digit n.sub.E of the memory to be processed                               are determined.                                                        P.sub.2 .....                                                                          ACC is loaded with "0" and ready to                                            introduce "0" into the least significant                                       digit position when the left shift opera-                                      tion is started.                                                       P.sub.3 .....                                                                          The exchange is carried out between ACC and                                    the memory and the digit address is                                            incremented to specify a one digit upper                                       position. The memory address is still at                                       m.sub.A. XD is repeated excuted through P.sub.4                                and P.sub.3. By the step ACC → M, "0" is                                transmitted from ACC to the least signifi-                                     cant digit position of the memory which                                        in turn provides its original contents for                                     ACC. When the digit address is up via P.sub.3                                  and XD is about to be executed at P.sub.3 via                                  P.sub.4, the second least significant digit is                                 selected to contain the original content                                       of the least significant digit position                                        which has previously been contained within                                     ACC. At this time ACC is allowed to                                            contain the contents of the second least                                       significant digit position. The most signifi-                                  cant digit is previously selected as n.sub.1.                                  If the transmission step reaches the                                           most significant digit position, BL = n.sub.1 is                               satisfied and P.sub.4 is skipped. In other                                     words, the digit contents are shifted                                          up to thereby conclude the processing of                                       Type 2.                                                                P.sub.4 .....                                                                          XI is repeated at P.sub.3 until BL = V.                                (VIII) PROCEDURE OF SETTING OR RESETTING A                                     ONE-BIT CONDITION F/F ASSOCIATED WITH A                                        SPECIFIC REGION OF THE MEMORY                                                  (Type 1)                                                                        ##STR34##                                                                     P.sub.1 .....                                                                          The file address m.sub.B and the digit                                         address n.sub.C of a region of the memory                                      to be processed are determined.                                        P.sub.2 .....                                                                          "1" is loaded into a desired bit N                                             within the digit position of the memory                                        specified by P.sub.1, thus concluding the process-                             ing of Type 1.                                                         (Type 2)                                                                        ##STR35##                                                                     P.sub.1 .....                                                                          The file address m.sub.B and the digit                                         address n.sub.C of a region of the memory                                      to be processed are determined.                                        P.sub.2 .....                                                                          "0" is loaded into a desired bit N within                                      the digit position of the memory specified                                     by P.sub.1, thus concluding the processing of                                  Type 2.                                                                (IX) PROCEDURE OF SENSING THE STATE OF THE                                     ONE-BIT CONDITIONAL F/F ASSOCIATED WITH A                                      SPECIFIC REGION OF THE MEMORY AND CHANGING                                     A NEXT PROGRAM ADDRESS (STEP) AS A RESULT OF                                   THE SENSING OPERATION                                                           ##STR36##                                                                     P.sub.1 .....                                                                          There are specified the file address m.sub.B                                   and the digit address n.sub.C where a desired                                  one-bit conditional F/F is present.                                    P.sub.2 .....                                                                          In the case where the contents of the bit                                      position (corresponding to the conditional                                     F/F) specified by N within the memory                                          region as selected during P.sub.1 assume "1",                                  the step proceeds to P.sub.4 with skipping P.sub.3,                            thus executing the operation OP.sub.1. In                                      the event that the desired bit position                                        bears "0", the next step P.sub.3 is skipped.                           P.sub.3 .....                                                                          When the foregoing P.sub.2 has been concluded                                  as the conditional F/F in the "0" state,                                       the program step P.sub.n is selected in order                                  to execute the operation OP.sub.2.                                     (X) PROCEDURE OF DECIDING WHETHER THE DIGIT                                    CONTENTS OF A SPECIFIC REGION OF THE MEMORY                                    REACH A PRESELECTED NUMERAL AND ALTERING A                                     NEXT PROGRAM ADDRESS (STEP) ACCORDING TO THE                                   RESULTS OF THE DECISION                                                         ##STR37##                                                                     P.sub.1 .....                                                                          The region of the memory which contains                                        contents to be decided is identified by                                        the file address m.sub.B and the digit                                         address n.sub.C.                                                       P.sub.2 .....                                                                          The contents of the memory as identified                                       during P.sub.1 are unloaded into ACC.                                  P.sub.3 .....                                                                          The contents of ACC are compared with                                          the preselected value N and if there is                                        agreement the step advances toward P.sub.5                                     without executing P.sub.4 to perform the                                       operation OP.sub.1. P.sub.4 is however reached                                 if the contents of ACC are not equal to N.                             P.sub.4 .....                                                                          The program address (step) P.sub.n is then                                     selected to perform the operation OP.sub.2.                            (XI) PROCEDURE OF DECIDING WHETHER THE                                         PLURAL DIGIT CONTENTS OF A SPECIFIC REGION OF                                  THE MEMORY ARE EQUAL TO A PRESELECTED                                          NUMERAL AND ALTERING A PROGRAM STEP                                            ACCORDING TO THE RESULTS OF THE DECISION                                        ##STR38##                                                                     P.sub.1 .....                                                                          The region of the memory to be judged                                          is identified by the file address m.sub.B and                                  the first digit address n.sub.E.                                       P.sub.2 .....                                                                          The value N is loaded into ACC for                                             comparison.                                                            P.sub.3 .....                                                                          The value V within ACC is compared                                             with the digit contents of the specific                                        region of the memory and if there is                                           agreement P.sub.5 is reached without passing                                   P.sub.4 to advance the comparison operation                                    toward the next succeeding digit. P.sub.4                                      is selected in a non-agreement.                                        P.sub.4 .....                                                                          In the case of a non-agreement during                                          P.sub.3 the program address (step) P.sub.n is                                  specified to execute the operation                                             forthwith.                                                             P.sub.5 .....                                                                          The digit address is incremented by                                            adding "1" thereto. This step is aimed                                         at evaluating in sequence a plurality of                                       digits within the memory. The ultimate                                         digit to be evaluated is previously deter-                                     mined as (V). The comparison is repeated                                       throughout the desired digit positions. If                                     a non-agreement state occurs on the way,                                       the operation OP.sub.2 is accomplished                                         through P.sub.4. In the case where the agree-                                  ment state goes on till BL = V, there                                          is selected P.sub.7 rather than P.sub.6 to perform                             the operation OP.sub.1.                                                P.sub.6 .....                                                                          When the agreement state goes on during                                        P.sub.5, P.sub.3 is reverted for evaluation.                           (XII) PROCEDURE OF DECIDING WHETHER THE                                        CONTENTS OF A SPECIFIC REGION OF THE MEMORY                                    ARE SMALLER THAN A GIVEN VALUE AND DECIDING                                    WHICH ADDRESS (STEP) IS TO BE EXECUTED                                          ##STR39##                                                                     P.sub.1 .....                                                                          The file address m.sub.B and the digit                                         address n.sub.C of the memory are decided.                             P.sub.2 .....                                                                          The contents of the memory as specified                                        during P.sub.1 are unloaded into ACC.                                  P.sub.3 .....                                                                          N is the value to be compared with the                                         contents of the memory and the operand                                         area specifies 16 - N which in turn is                                         added to the contents of ACC, the sum                                          thereof being loaded back to ACC. The                                          occurrence of a fourth bit carry during                                        the addition suggests that the result                                          of the binary addition exceeds 16,                                             that is, M + (16 - N)≧16 and hence                                      M ≧ N. The step is progressed toward P.sub.4.                   P.sub.4 .....                                                                          When M ≧ N is denied, the program step                                  P.sub.n is selected to carry out the operation                                 OP.sub.2.                                                              (XIII) PROCEDURE OF DECIDING WHETHER THE                                       CONTENTS OF A SPECIFIC REGION OF THE MEMORY                                    ARE GREATER THAN A GIVEN VALUE AND DECIDING                                    WHICH ADDRESS (STEP) IS TO BE EXECUTED                                          ##STR40##                                                                     P.sub.1 .....                                                                          The file address m.sub.B and the digit                                         address n.sub.C of the memory are decided.                             P.sub.2 .....                                                                          The contents of the memory as specified                                        during P.sub.1 are unloaded into ACC.                                  P.sub.3 .....                                                                          N is the value to be compared with the                                         contents of the memory and the operand                                         area specifies 15 - N which in turn is added                                   to the contents of ACC, the sum thereof                                        being loaded back to ACC. The occurrence                                       of a fourth bit carry during the addition                                      suggests that the results of binary                                            addition exceeds 16, that is,                                                  M + (15 - N) ≧ 16 and hence M ≧ N + 1 and                        M > N. The step is progressed toward P.sub.5                                   with skipping P.sub.4, thus performing the                                     operation OP.sub.1. In the absence of a                                        carry (namely, M > N) the step P.sub.4 is                                      reached.                                                               P.sub.4 .....                                                                          When M≧N is denied, the program address                                 (Step) P.sub.n is selected to carry out the                                    operation OP.sub.2.                                                    (XIV) PROCEDURE OF DISPLAYING THE CONTENTS OF                                  A SPECIFIC REGION OF THE MEMORY                                                (Type 1)                                                                        ##STR41##                                                                     P.sub.1 .....                                                                          The bit number n.sub.1 of the buffer register                                  W is loaded into ACC to reset the                                              overall contents of the buffer register                                        W for generating digit selection signals                                       effective to drive a display panel on a                                        time sharing basis.                                                    P.sub.2 .....                                                                          After the overall contents of the register                                     W are one bit shifted to the right, its                                        first bit is loaded with "0". This                                             procedure is repeated via P.sub.4 until C.sub.4 = 1                            during P.sub.3, thus resetting the overall                                     contents of W.                                                         P.sub.3 .....                                                                          The operand I.sub.A is decided as "1111" and                                   AC + 1111 is effected (this substantially                                      corresponds to ACC-1). Since ACC is                                            loaded with n.sub.1 during P.sub.1, this process                               is repeated n.sub.1 times. When the addition                                   of " 1111" is effected following ACC = 0,                                      the fourth bit carry C.sub.4 assumes "0". When                                 this occurs, the step is advanced to P.sub.4.                                  Otherwise the step is skipped up to P.sub.5.                           P.sub.4 .....                                                                          When the fourth bit carry C.sub.4 = 0 during                                   ACC + 1111, the overall contents of W                                          are reduced to "0" to thereby complete                                         all the pre-display processes. The first                                       address P.sub.6 is set for the memory display                                  steps.                                                                 P.sub.5 .....                                                                          In the event that the fourth bit carry C.sub.4 = 1                             during ACC + 1111, the overall contents                                        of W have not yet reduced to "0". Under                                        these circumstances P.sub.2 is reverted to                                     repeat the introduction of "0" into W.                                 P.sub.6 .....                                                                          The first digit position of the memory                                         region which contains data to be displayed                                     is identified by the file address m.sub.A and                                  the digit address n.sub.A.                                             P.sub.7 .....                                                                          After the contents of the register W for                                       generating the digit selection signals                                         are one bit shifted to the right, its                                          first bit position is loaded with "1"                                          and thus ready to supply the digit selec-                                      tion signal to the first digit position                                        of the display.                                                        P.sub.8 .....                                                                          The contents of the specific region of the                                     memory are unloaded into ACC. The file                                         address of the memory still remains at                                         m.sub.A, whereas the digit address is decremented                              for the next succeeding digit processing.                              P.sub.9 .....                                                                          The contents of the memory is shifted                                          from ACC to the buffer register F. The                                         contents of the register F are supplied to                                     the segment decoder SD to generate segment                                     display signals.                                                       P.sub.10 .....                                                                         To lead out the contents of the register                                       W as display signals, the conditional F/F                                      N.sub.p is supplied with "1" and placed into                                   the set state. As a result of this, the                                        contents of the memory processed during P.sub.9                                are displayed on the first digit position                                      of the display.                                                        P.sub.11 .....                                                                         A count initial value n.sub.2 is loaded into                                   ACC to determine a one digit long display                                      period of time.                                                        P.sub.12 .....                                                                         ACC-1 is carried out like P.sub.3. When ACC                                    does not assume "0" (when C.sub.4 = 1) the                                     step is skipped up to P.sub.14.                                        P.sub.13 .....                                                                         A desired period of display is determined                                      by counting the contents of ACC during P.sub.12.                               After the completion of the counting P.sub.15 is                               reached from P.sub.13. The counting period                                     is equal in length to a one-digit display                                      period of time.                                                        P.sub.14 .....                                                                         Before the passage of the desired period                                       of display the step is progressed from P.sub.12                                to P.sub.14 with skipping P.sub.13 and jumped back                             to P.sub.12. This procedure is repeated.                               P.sub.15 .....                                                                         N.sub.p is reset to stop supplying the digit                                   selection signals to the display. Until                                        N.sub.p is set again during P.sub.10, overlapping                              display problems are avoided by using the                                      adjacent digit signals.                                                P.sub.16 .....                                                                         The register W is one bit shifted to the                                       right and its first bit position is loaded                                     with "0". "1"  introduced during P.sub.7 is                                    one bit shifted down for preparation of the                                    next succeeding digit selection.                                       P.sub.17 .....                                                                         It is decided whether the ultimate digit                                       of the memory to be displayed has been                                         processed and actually whether the value                                       n.sub.E of the last second digit has been                                      reached because the step P.sub.8 of B.sub.L - 1 is                             in effect.                                                             P.sub.18 .....                                                                         In the event that ultimate digit has not                                       yet been reached, P.sub.8 is reverted for the                                  next succeeding digit display processing.                              P.sub.19 .....                                                                         For example, provided that the completion                                      of the display operation is conditional by                                     the flag F/F FA, FA = 1 allows P.sub.20 to be                                  skipped, thereby concluding all the display-                                   ing steps.                                                             P.sub.20 .....                                                                         If FA = 1 at P.sub.19, the display steps are                                   reopened from the first display and the                                        step is jumped up to P.sub.6.                                          (Type 2)                                                                        ##STR42##                                                                     P.sub.1 .....                                                                          The bit number n.sub.1 of the buffer register                                  W is loaded into ACC to reset the overall                                      contents of the buffer register W for                                          generating digit selection signals                                             effective to drive a display panel on a                                        time sharing basis.                                                    P.sub.2 .....                                                                          After the overall contents of the register                                     W are one bit shifted to the right, its                                        first bit is loaded with "0". This pro-                                        cedure is repeated via P.sub.4 until C.sub.4 = 1                               during P.sub.3, thus resetting the overall con-                                tents of W.                                                            P.sub.3 .....                                                                          The operand I.sub.A is decided as "1111" and AC +                              1111 is effected (this substantially                                           corresponds to ACC-1). Since ACC is loaded                                     with n.sub.1 during P.sub.1, this process is                                   repeated n.sub.1 times. When the addition of                                   "1111" is effected following ACC = 0, the                                      fourth bit carry C.sub.4 assumes "0". When this                                occurs, the step is advanced to P.sub.4. Other-                                wise the step is skipped up to P.sub.5.                                P.sub.4 .....                                                                          When the fourth bit carry C.sub.4 = 0 during                                   ACC + 1111, the overall contents of W                                          are reduced to "0" to thereby complete all                                     the pre-display processes. The first                                           address P.sub.6 is set for the memory display                                  steps.                                                                 P.sub.5 .....                                                                          In the event that the fourth bit carry                                         C.sub.4 = 1 during ACC + 1111, the overall                                     contents of W have not yet reduced to                                          "0". Under these circumstances P.sub.2 is                                      reverted to repeat the introduction of                                         "0" into W.                                                            P.sub.6 .....                                                                          The upper four bits of the first digit                                         position of the memory region which                                            contains data to be displayed are identified                                   by the file address m.sub.A and the digit address                              m.sub.A.                                                               P.sub.7 .....                                                                          The contents of the specific region of                                         the memory are unloaded into ACC. The                                          file address of the memory still remains                                       at m.sub.A, whereas the digit address is                                       decremented to specify the lower four bits.                            P.sub.8 .....                                                                          The contents of ACC, the upper four bits,                                      are transmitted into the temporary register                                    X.                                                                     P.sub.9 .....                                                                          The contents of the specific region of the                                     memory are unloaded into ACC. The file                                         address of the memory still remains at                                         m.sub.A, whereas the digit address is decremented                              to specify the upper four bits of the next                                     succeeding digit.                                                      P.sub.10 .....                                                                         The contents of ACC are unloaded into                                          the stack register SA and the contents of                                      the temporary register X into the stack                                        register SX.                                                           P.sub.11 .....                                                                         After the contents of the register W for                                       generating the digit selection signals                                         are one bit shifted to the right, its                                          first bit position is loaded with "1" and                                      thus ready to supply the digit selection                                       signal to the first digit position of the                                      display.                                                               P.sub.12 .....                                                                         To lead out the contents of the register                                       W as display signals, the conditional F/F                                      N.sub.p is supplied with "1" and placed into                                   the set state. As a result of this, the                                        contents of the memory processed during                                        P.sub.10 are displayed on the first digit posi-                                tion of the display.                                                   P.sub.13 .....                                                                         A count initial value n.sub.2 is loaded into                                   ACC to determine a one digit long display                                      period of time.                                                        P.sub.14 .....                                                                         ACC - 1 is carried out like P.sub.3. When                                      ACC assumes "0" P.sub.15 is reached and when                                   ACC ≠ 0 (when C.sub.4 = 1) the step is skipped                           up to P.sub.16. This procedure is repeated.                            P.sub.15 .....                                                                         A desired period of display is determined                                      by counting the contents of ACC during                                         P.sub.14. After the completion of the counting                                 P.sub.17 is reached from P.sub.15. The counting                                period is equal in length to a one-digit                                       display period of time.                                                P.sub.16 .....                                                                         Before the passage of the desired period                                       of display the step is progressed from                                         P.sub.14 to P.sub.16 with skipping P.sub.15 and                                jumped back to P.sub.14. This procedure is                                     repeated.                                                              P.sub.17 .....                                                                         N.sub.p is reset to stop supplying the digit                                   selection signals to the display. Until                                        N.sub.p is set again during P.sub.10, overlapping                              display problems are avoided by using the                                      adjacent digit signals.                                                P.sub.18 .....                                                                         The register W is one bit shifted to                                           the right and its first bit position is                                        loaded with "0". "1" introduced during                                         P.sub.7 is one bit shifted down for prepara-                                   tion of the next succeeding digit selection.                           P.sub.19 .....                                                                         It is decided whether the ultimate digit                                       of the memory to be displayed has been                                         processed and actually whether the value                                       n.sub.E of the last second digit has been                                      reached because the step p.sub.9 of B.sub.L - 1 is in                          effect.                                                                P.sub.20 .....                                                                         In the event that ultimate digit has not                                       yet been reached, P.sub.7 is reverted for the                                  next succeeding digit display processing.                              (XV) PROCEDURE OF DECIDING WHICH KEY SWITCH                                    IS ACTUATED (SENSING ACTUATION OF ANY KEY                                      DURING DISPLAY)                                                                 ##STR43##                                                                      ##STR44##                                                                      ##STR45##                                                                     P.sub.1 -P.sub.18 ..                                                                   The display processes as discussed in                                          (XIV) above.                                                           P.sub.19 .....                                                                         After the overall digit contents of the                                        register W are displayed, the flag F/F                                         FC is set to hold all the key signals I.sub.1 -                                I.sub.n at a "1" level.                                                P.sub.20 .....                                                                         The step is jumped to P.sub.30 as long as any                                  one of the keys connected to the key input                                     KN.sub.1 is actuated.                                                  P.sub.22 -P.sub.27 ..                                                                  It is decided whether any one of the keys                                      each connected to the respective key inputs                                    KN.sub.2 -KF.sub.2 and in the absence of any                                   actuation the step is advanced toward the                                      next succeeding step. To the contrary, the                                     presence of the key actuation leads to                                         P.sub.30.                                                              P.sub.28 .....                                                                         When any key is not actuated, F/F FC is                                        reset to thereby complete the decision as                                      to the key actuations.                                                 P.sub.29 .....                                                                         The step is jumped up to P.sub.6 to reopen the                                 display routine.                                                       P.sub.30 .....                                                                         When any key is actually actuated, the                                         memory digit address is set at n.sub.1 to                                      generate the first key strobe signal I.sub.1.                          P.sub.31 .....                                                                         It is decided if the first key strobe                                          signal I.sub.1 is applied to the key input KN.sub.1                            and if not the step is advanced toward P.sub.33.                       P.sub.32 .....                                                                         When the first key strobe signal I.sub.1 is                                    applied to the key input KN.sub.1, which kind                                  of the keys is actuated is decided. There-                                     after, the step is jumped to P.sub.A to provide                                proper controls according to the key                                           decision. After the completion of the                                          key decision the step is returned directly                                     to P.sub.1 to commence the displaying operation                                again (P.sub.Z is to jump the step to P.sub.1)                         P.sub.33 -P.sub.38 .....                                                               It is sequentially decided whether                                             the keys coupled with the first key strobe                                     signal I.sub.1 are actuated. If a specific key                                 is actuated, the step jumps to P.sub.B -P.sub.D                                for providing appropriate controls for                                         that keys.                                                             P.sub.39 .....                                                                         This step is executed when no key coupled                                      with the first key strobe signal I.sub.1.                                      This step is to increment the digit add-                                       ress of the memory for the developments                                        of the key strobe signals.                                             P.sub.41 and up                                                                        ..... The appropriate key strobe                                               signals are developed and KN.sub.1 -KF.sub.2 are                               sequentially monitored to decide what                                          kind of the keys are actuated. Desired                                         steps are then selected to effects                                             control steps for those actuated keys.                                 P.sub.A and up                                                                         ..... Control steps for the first actua-                                       ted keys.                                                              P.sub.X .....                                                                          P.sub.1 is returned to reopen the display opera-                               tion after the control steps for the first                                     key.                                                                   ______________________________________                                    

The foregoing is the description of the respective major processing events in the CPU architecture.

By reference to a flow chart of FIG. 6 an example of the display operation of a calculator implementing the display device according to the preset invention will now be described in detail.

In FIG. 6, n₁ represents the step of executing operations programmed by the operator and n₂ the step of checking if the calculator is in a halt. Unless the calculator is in a halt n₁ ⃡n₂ are repeated. The halt condition used herein means that a particular calculation comes to a halt until data are entered at the step of entering data from outside of the calculator on the way of executing the particular calculation. If the halt condition is reached, n₂ →n₃ so that a given value N₁ is sent to a counter CO which is built in a specific region of RAM. During the step n₄ the results MX of calculations (or running results) are displayed. The step n₅ is effected to check if the count of the counter CO is "0". If CO≠0, then the step n₆ is effected to subtract "1" from the count of the counter CO. In other words, a cycle of the steps n₄ →n₅ →n.sub. 6 →n₄ →n₅ →is repeated N₁ +1 times, displaying MX for a given period of time (say, 5 sec). Thereafter, when the count of the counter CO reaches "0", n₅ →n₇ to add "1" to a counter R which is part of RAM.

Assume now that the counter R is reset to "0". R contains the recoveries of the halt condition. During n₈ suppress codes CS are loaded into a character memory MC which occupies a specific region of RAM and contains characters each having 8 bit codes. The purpose of the suppress codes CS is to keep the display from displaying anything, for example, encoded as "11111111". During n₉ the character generator MC is allowed to contain codes indicative of "DE (τ)" at its first digit position. n₁₀ is then executed to load the count of a program counter P_(L) within ROM plus "1" into the program stack register SP. cf. the instruction code No. 54 which is to specify its home address with the aid of the return RIT instruction No. 55. Then, n₁₀ →n₂₆ to load a given value N₂ into the counter CO within RAM. During n₂₇ the contents of the character generator MC are displayed. n₂₈ follows to check if the count of the counter CO reaches "0" and if CO≠0 the step n₂₉ tekes place to subtract "1" from the count of the counter CO. Whether there is any key input applied is decided during n₃₀ and in the absence of any key actuation the steps are linked as n₃₀ → n₂₇. In other words, a chained cycle of n₂₇ →n₂₈ →n₂₉ →n₃₀ →n₂₇ and so on is repeated N₂ +1 times, in which case the displaying operation goes on for a given length of time. After that n₂₈ →n₃₁, thus shifting the visual display of the contents of the character memory MC to the left by the one digit length. The step n₃₂ is to determine whether the conditional F/F A (part of RAM) is in the set or reset state. F/F A is set during n₃₅ after all data are stored into the character memory MC, thus deciding whether the display of the data (FIGS. 2(b) through 2(f)) has been completed. In this instance, with F/F A in the reset state, n₃₂ →n₃₃ and then step n₁₁ is reached through the return (RIT) instruction. The step n₁₁ corresponds to the count of the program counter P_(L) in ROM stored pursuant to the TML instruction at n₁₀. In this manner, the visual display indicative of "DE ()" is completed as viewed from FIG. 2(b) through the steps n₉ →n₁₀ →n₂₆ →n₂₇ →n₂₈ →n₂₇ →n₃₀ →n₂₇ →n₂₈ . . . →n₃₁ →n₃₂ →n₃₃. A sequence of the operating steps n₁₁ →n₁₂ →n₂₆ →n₂₇ →n₂₈ →n₂₉ →n₃₀ →n₂₇ →n₂₈ →n₃₁ →n₃₂ →n₃₃ provides a visual display of "DEH ( )" as shown in FIG. 2(c). Likewise, a sequence of the operating steps of n₁₅ →n₁₆ →n₂₆ → n₂₇ →n₂₈ →n₂₉ n₃₀ →n₂₇ →n₂₈ →n₃₁ →n₃₂ →n₃₃ provides a visual display of "DEHTA (- )".

Subsequently, the step is advanced from n₃₃ to n₁₇ to store the step to be returned through the RIT instruction and n₁₇ →n₃₈ to monitor the count of the counter R.

When R=1 particularly under the first halt condition at n₇, n₃₈ →n₄₄ to allow the character memory MC to contain at its first digit position codes indicative of "A". Through the developments of n₄₄ →n₄₅ →n₁₈, the step n₁₉ to be returned through the return instruction is recalled, followed by the step n₂₆. Therefore, a visual display of "DEHTA A (- A)" is provided through n₄₄ →n₄₅ →n₁₈ →n₂₆ →n₂₇ →n₂₈ →n₂₉ →n₃₀ →n₂₇ →n₂₈ →n₃₁ →n₃₂ →n₃₃.

In the foregoing manner, the contents of the character memory are visually displayed while the contents of the character memory are progressively shifted and a new character to be displayed is loaded into its first digit position, as viewed from FIGS. 2(b) through 2(f). After the display is completed as indicated in FIG. 2(f), the step n₃₅ becomes operative through the return instruction, in which the conditional F/F A is forced into the set state. During the next step n₃₆ the suppress codes CS are contained at the first digit position of the character generator MC, which codes establishes a boundary between different two displaying contents. The step n₃₇ is carried out to decide whether the overall digits within the character generator MC assume the suppress codes CS. The decision as to MC=CS is aimed at beginning the display operation with the head of the contents to be displayed after the overall digits are shifted off on the display panel. Since in this case the overall digit assume no suppress codes, n₃₇ →n₂₆ to enable a display as shown in FIG. 2(g). Thereafter, the contents of the character memory are shifted during n₃₁ and allowed to contain the suppress codes during n₃₆. As a result, the displaying contents are gone from the extreme left end of the display panel. Provided that the memory character is filled completely with the suppress codes, n₃₆ →n₃₇ →n₉ to repeat the display operation. In other words, "DEHTA A WO IREYO ( A and INSERT DATA A in its English version)" is visually repeatedly displayed.

Since the operator has completed the program for the calculation at the step n₁ under these circumstances, he then inserts the data A via the keys. The step n₃₀ recognizes that there has actually been the key input, returning to the steps n₁. The calculation routine is reopened with the step n₁ according to the newly keyed data.

Then, if the calculator comes to a halt again, then n₂ n₃ and the instantaneous calculation results are displayed for a given length of time via the chained steps of n₄ →n₅ →n₆ →n₄ in the same way as in the first halt condition. "1" is added to the counter R during n₇. In this case R=2. Likewise the first halt condition the same steps are repeated up to n₁₇, followed by n₃₈ →n₃₉ →n₄₃ in which codes representative of "B" are loaded into the character memory MC during n₄₃. Therefore, "DEATH B WO IREYO (INSERT DATA B in its English version)" is displayed under the second halt condition. Similarly, "DEHTA C WO IREYO (INSERT DATA C in its English version)" is displayed under the third halt condition and "DEHTA D WO IREYO" under the fourth halt condition.

FIG. 7 is a flow chart of a subroutine ##STR46## shown in FIG. 6. The conditional F/F B (part of RAM) is reset during the step n_(a) and the contents of the character memory MC are 4 bits shifted to the left during the step n_(b). The step n_(c) is effected to monitor the state the flip flop B, followed by the step n_(d) of setting the flip flop B. During the step n_(b) the character memory MC is shifted 4 bits to the left again. This subroutine ends with the next succeeding monitoring of the flip flop B. Since each of the characters contained within the character memory MC has 8 bits, MC is shifted one character by repeating the 4 bit long shift operation twice.

It is obvious that the respective processing events depicted in FIGS. 6 and 7 can be executed according appropriate subcombinations of the above defined functional operations accomplished by the CPU architecture. Table 3 shows the relationship between the processing events depicted in FIG. 6 and the functional operations accomplished by the CPU architecture. The processing list numbers correspond to the above described functional procedures (I) through (XV).

                  TABLE 3                                                          ______________________________________                                                 processing             processing                                      step    list No.      step     list No.                                        ______________________________________                                         n.sub.1               n.sub.21 (II) Type 1                                     n.sub.2 (IX)          n.sub.22                                                 n.sub.3 (II) Type 1   n.sub.23 (II) Type 1                                     n.sub.4 (XIV) Type 1  n.sub.24                                                 n.sub.5 (X)           n.sub.25 (II) Type 1                                     n.sub.6 (V) Type 9    n.sub.26 (II) Type 1                                     n.sub.7 (V) Type 9    n.sub.27 (XIV) Type 2                                    n.sub.8 (I) Type 1    n.sub.28 (X)                                             n.sub.9 (II) Type 1   n.sub.29 (V) Type 9                                      n.sub.10              n.sub.30 (XV)                                            n.sub.11                                                                               (II) Type 1   n.sub.31 FIG. 5                                          n.sub.12              n.sub.32 (IX)                                            n.sub.13                                                                               (II) Type 1   n.sub.33                                                 n.sub.14              n.sub.34                                                 n.sub.15                                                                               (II) Type 1   n.sub.35 (VIII) Type 1                                   n.sub.16              n.sub.36 (II) Type 1                                     n.sub.17              n.sub.37 (XI)                                            n.sub.18              n.sub.38 (X)                                             n.sub.19              n.sub.39 (X)                                             n.sub.20              n.sub.40 (X)                                                                   n.sub.41 (II) Type 1                                                           n.sub.42 (II) Type 1                                                           n.sub.43 (II) Type 1                                                           n.sub.44 (II) Type 1                                                           n.sub.45                                                 ______________________________________                                    

As is clear from Table 3, the respective steps in FIG. 6 are accomplished by the functional operations of the CPU architecture. The steps n₁, n₁₀, n₁₂, n₁₄, n₁₆ -n₁₈, n₂₀, n₂₂, n₂₄, n₃₃ and n₃₄ are easily understood from the disclosure of the CPU architecture.

Table 4 depicts the relationship between the respective steps of shifting the character memory MC to the left and the functional operations of the CPU architecture.

                  TABLE 4                                                          ______________________________________                                         step              processing list No.                                          ______________________________________                                         n.sub.a           (VIII) Type 2                                                n.sub.b           (VII) Type 2                                                 n.sub.c           (IX)                                                         n.sub.d           (VIII) Type 1                                                ______________________________________                                    

Similarly, the MC left shift operation can be accomplished by the respective steps as is clear from Table 4.

As noted earlier, the present invention makes the CPU architecture which interprets and executes the various instructions, available for the displaying purposes in electronic calculators and so forth.

Whereas the present invention has been described with respect to a specific embodiment, it will be understood that various changes and modifications will be suggested to one skilled in the art, and it is intended to encompass such changes and modifications as fall within the scope of the appended claims. 

We claim:
 1. An electronic calculator comprising:calculating means for performing arithmetic operations and for producing an output representative of the results of these operations; prompting means for generating signals representative of operating instructions for instructing the user of procedures used by said calculating means; a multiple character display; first means for converting the output of said calculating means into a display signal to statically display the results of said arithmetic operations of said multiple character display; and second means for converting the signals generated by said prompting means into alphanumeric display signals to generate a running display of said operating instructions on said multiple character display.
 2. The calculator of claim 1 wherein said second means for converting allows said display to display instructions having a greater length than the capacity of said display.
 3. The calculator of claim 2 wherein said multiple character display includes a plurality of display segments; andwherein said second means for converting includes a means for repetitively shifting the instructions being displayed across said display by sequentially shifting a display signal from one display segment to an adjacent display segment.
 4. The calculator of claim 3 wherein said means for repetitively shifting includes means for circulating the displayed instructions to wrap the portion of the instructions running off one end of the display around to redisplay that portion by shifting that portion back onto the other end of the display after the total operating instruction is displayed.
 5. The calculator of claim 4 wherein said second means for converting may also generate a static display of said operating instructions.
 6. The calculator of claim 3 wherein each display segment is a dot matrix display.
 7. The calculator of claim 3 wherein said means for repetitively shifting is formed by a central processing unit (CPU) having a read only memory and a random access memory.
 8. The calculator of claim 3 wherein said second means for converting further includes means for suppressing a portion of said display panel nearest the end from which the instructions run off.
 9. The calculator of claim 7 wherein said instructions to be displayed are stored within a portion of said random access memory, the information stored within said memory being shifted to shift the instructions across said display.
 10. A processor comprisingdata derivation means for producing desired data in response to a user's control, said desired data being processed by said data derivation means to provide an answer to a user generated query; prompting means for generating signals indicative of operating instructions for instructing the user of procedures used by said data derivation means; a multiple character display; first means for converting said desired data from said data derivation means into a display signal to statically display the answer to the user generated query on said multiple character display; and second means for converting the signals generated by said prompting means into alphanumeric display signals to generate a running display of said operating instructions on said multiple character display.
 11. The processor of claim 10 wherein said second means for converting allows said display to display instructions having a greater length than the capacity of said display.
 12. The processor of claim 11 wherein said multiple character display includes a plurality of display segments; andwherein said second means for converting includes a means for repetitively shifting the instructions being displayed across said display by sequentially shifting a display signal from one display segment to an adjacent display segment.
 13. The processor of claim 12 wherein said means for repetitively shifting includes means for circulating the displayed instructions to wrap the portion of the instructions running off one end of the display around to redisplay that portion by shifting that portion back onto the other end of the display after the total operating instruction is displayed.
 14. The processor of claim 13 wherein said second means for converting may also generate a static display of said operating instructions.
 15. The processor of claim 12 wherein each display segment is a dot matrix display.
 16. The processor of claim 12 wherein said means for repetitively shifting is formed by a central processing unit (CPU) having a read only memory and a random access.
 17. The processor of claim 12 wherein said second means for converting further includes means for suppressing a portion of said display nearest the end from which the instructions run off.
 18. The processor of claim 16 wherein said instructions to be displayed are stored within a portion of said random access memory, the information stored within said memory being shifted to shift the instructions across said display. 